Design of Digital Systems Lab
Course Name:
Design of Digital Systems Lab (CO204)
Programme:
B.Tech (CSE)
Semester:
Third
Category:
Programme Core (PC)
Credits (L-T-P):
02 (0-0-3)
Content:
Design of basic gates, Adders, Subtractors, Encoders, Decoders, Shifters: Up, Down, Up-Down, Counters, Flipflops, Code conversion, Multiplexers(All using behavioral modeling), Introduction to structural modeling, Adders, Subtractors, Multiplexors, Counters, Multiplier(array multiplier), Design of FSM: Moore machine, Melay machine.
References:
1. J. Bhasker, "VHDL primer", Third edition, Addison Wesley Longmen Singapore Pvt. Ltd.
2. Douglas Perry, "VHDL", McGraw Hill International, 1998.
3. Peter Ashenden, "The Designer Guide to VHDL", 1998.
Department:
Computer Science and Engineering